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TMP92CZ26A
92CZ26A-107
Sample 4) Calculation example for CPU + LDMA+ ARDMA + HDMA
Conditions:
CPU operation speed (f
SYS
) : 60 MHz
Display RAM : QVGA (320seg
× 240com)
Display quality : 65536 colors (TFT)
Refresh rate : 70 Hz (including 20 clocks of dummy cycles)
SDRAM Auto Refresh : Every 936 states (15.6
μs)
SDRAM : 16-bit width
HDMA : Transfers 5 Kbytes from internal RAM to I2S
Calculation example:
t
STOP
(LDMA) =((SegNum × K / 8) × tLRD) + (1 / f
SYS
[Hz])
= ((320 ×16 / 8) × 1 / f
SYS
[Hz] / 4) + (1 / f
SYS
[Hz])
= ((640) ×16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]
LHSYNC [period: s]
= 1/70 [Hz] /(COM+20 = 260) = 54.95 [μs]
t
STOP
(HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
SYS
[s] = 68 [μs]
LCD driver data transfer time [s]
= SegNum × (1/f
SYS
) × (LD bus transfer speed)
= 320 × (1/60 MHz) × 16 = 85 [μs]
Since LHSYNC [period: s] < LCD driver data transfer time [s], this setting is not possible.
When the transfer speed is changed to x4, the LCD driver data transfer time is calculated as follows:
(The transfer speed should be adjusted according to the required specifications.)
LCD driver data transfer time [s]
= SegNum × (1/f
SYS
) × (LD bus transfer speed)
= 320 × (1 / 60MHz) × 4 = 21.3 [μs]
LHSYNC [period: s]
− LCD driver data transfer time [s] − t
STOP
(LDMA)
= 54.95 [μs] − 21.3 [μs] − 2.68 [μs] = 30.94 [μs]
To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time) must
be set to 30.92 [
μS] or less. Although transferring all 5 Kbytes from the internal RAM to I2S requires t
STOP
(HDMA) = 68
[
μs], the maximum HDMA time should be limited by using the HDMATR register.