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TMP92CZ26A
92CZ26A-561
3.19.5.3 Considerations for Using the LCDC
1 If the operation mode is changed while the LCDC is operating, a maximum of
one frame may not be displayed properly. Although this degree of disturbance
does not normally pose any problem (e.g. no response on LCD, display not
visible to human eyes), the actual operation largely depends on the conditions
such as the LCD driver, LCD panel, and frame frequency to be used. It is
therefore recommended that operation checks be performed under the actual
conditions.
2 The LCDMODE1<LDC2:0> setting must not be changed while the LCDC is
operating. Be sure to set LCDCTL0<START> to “0” to stop the LCDC operation
before changing <LDC2:0>.
3 The LCDC obtains the bus from the CPU when it has some operation to
perform. Since the TMP92CZ26A includes other units that act as bus masters
such as HDMA and SDRAMC, it is necessary to estimate the bus occupancy
rate of each bus master in advance. For details, see the chapter on HDMA.