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TMP92CZ26A
92CZ26A-213
3.9.2.5 DMA-function bank register
In addition to functioning as read/write function of CPU, this LSI can also function which
transfer data at high-speed by internal DMAC becoming bus master. (Please refer to DMAC
section)
In Bank for only DMA that different from Bank for CPU or LCDC display data, although
condition of program bank, read-bank and write-bank for CPU, bank of Source address and
Destination address are enable during operate DMA.
DMAC which assignment is possible in this LSI is 5-channel. But bank controller is 2-type.
Even-channel of DMA-channel 0, 2 and 4 become E-group (ES and ED group), odd-channel of
DMA-channel 1and 3 become O-group (OS and OD group). Assignment every channel is disable
in same group.
Following shows examples of setting bank for DMA_Source address to 1 in LOCALX area and
setting bank for DMA_Destination address to 2 in LOCALY area. If Source address which set to
XXX by using DMA function was set to LOCALX-area and Destination address was set to
LOCALY-area, when DMA of channel 0 is start, LOCALX bank1 is set to source and LOCALY
bank2 is set to destination.
(Example)
ldw (localesx), 8001h ; Set DMA source bank for channel 0
ldw (localedy), 8002h ; Set DMA destination bank for channel 0
DMA channel 0 start