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TMP92CZ26A
92CZ26A-316
3.14.1 Block Diagram
Figure 3.14.2 Block Diagram
Selector
φT0
φT2
φT8
φT32
SC0MOD0
<SC1:0>
Receive buffer 1 (Shift register)
RXDCLK
SC0MOD0
<CTSE>
Prescaler
Selector
TA0TRG
(from TMRA0)
UART
mode
BR0CR
<BR0S3:0>
Baud rate generator
Selector
SC0MOD0
<SM1:0>
Selector
÷2
I/O interface mode
SC0CR
<IOC>
Receive counter
(UART only ÷ 16)
Transmision
counter
(UART only ÷ 16)
Receive
control
Transmission
control
INTRX0
INTTX0
Receive buffer 2 (SC0BUF)RB8 Error flag
SC0CR
<OERR> <PERR> <FERR>
Serial channel
interrupt control
TB8
CTS0
TXD0
Transmission buffer (SC0BUF)
RXD0
TXDCLK
SC0MOD0
<WU>
f
IO
SC0MOD0
<RXE>
SCLK0
SCLK0
SIOCLK
Internal data bus
Parity control
SC0CR
<PE> <EVEN>
Serial clock generation circuit
BR0CR<BR0CK1:0>
BR0ADD
<BR0K3:0>
BR0CR
<BR0ADDE>
I/O interface mode
φT0
2 64 4 8 16 32
Prescale
r
φT2 φT8 φT32
INT request