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TMP92CZ26A
92CZ26A-573
3.20.6 Note
1. De-bounce circuit
The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not
operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an
interrupt which through the de-bounce circuit is not generated.
When started from IDLE1, STOP or PCM mode by using TSI, set the de-bounce circuit to
disable before a condition become to HALT or PCM mode. (TSICR1<DBC7>="0")
2. Port setting
During conversion the middle voltage of 0V~AVcc by using AD converter, the middle
voltage is inputted to a normal C-MOS input-gate (P96 and P97), too.
Therefore, provide the flow current for P96 and P97 by using TSICR0<INGE>. In this case
(TSICR0<INGE>="1"), when the input to C-MOS logic is cut, TSICR0<PTST> for confirming
a first pen touch is always set to “1”. Please be careful.