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TMP92CZ26A
92CZ26A-274
3.12.3 SFR
TMRA01 RUN Register
7 6 5 4 3 2 1 0
Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN
Read/Write R/W R/W
After Reset 0 0 0 0 0
TMRA01
prescaler
Up counter
(UC1)
Up counter
(UC0)
Function
Double
buffer
0: Disable
1: Enable
In IDLE2
mode
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
Note: The values of bits 4 to 6 of TA01RUN are “1” when read.
TMRA23 RUN Register
7 6 5 4 3 2 1 0
Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN
Read/Write R/W R/W
After Reset 0 0 0 0 0
TMRA23
prescaler
Up counter
(UC3)
Up counter
(UC2)
Function
Double
buffer
0: Disable
1: Enable
In IDLE2
mode
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
Note: The values of bits 4 to 6 of TA23RUN are “1” when read.
Figure 3.12.6 Register for TMRA (1)
TA01RUN
(1100H)
TA0REG double buffer control
0 Disable
1 Enable
Count control
0 Stop and clear
1 Run (Count up)
TA23RUN
(1108H)
TA3REG double buffer control
0 Disable
1 Enable
Count control
0 Stop and clear
1 Run (Count up)