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TMP92CZ26A
92CZ26A-392
FIFO_DISABLE (Bit1)
0: FIFO enabled
1: FIFO disabled
This bit symbol shows FIFO status except EP0.
If the FIFO is set to disabled, the UDC transmits NA
K
handshake forcibly for the all transfer. Disabled or enabled is set
by COMMAND register. This bit is cleared to “0” when transfer
type is changed.
STAGE_ERROR (Bit0)
0: SUCCESS
1: ERROR
This bit symbol shows that status stage is not terminated
correctly. ERROR is set when a status stage is not terminated
correctly and new SETUP token is received.
When this bit is “1”, this bit is cleared to “0” by read
EP0_STATUS register. This bit is not cleared even if normal
control transfer or other transfer is executed after. To clear, read
this bit. When software transaction is finished and UDC writes
EOP register, UDC shifts to status register and waits
termination of status stage. In this case, if software is needed to
confirm that status stage is terminated correctly, when a new
request flag is received, it can be confirmed that whether last
request terminate correctly or not. And during request routine in
software, when new request flag is asserted, it can be confirmed
that whether last request is canceled or not halfway.