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TMP92CZ26A
92CZ26A-602
AD Conversion Result Register 4 Low
7 6 5 4 3 2 1 0
bit Symbol ADR41 ADR40 OVR4 ADR4RF
Read/Write R R R
After reset 0 0 0 0
Function Store Lower 2 bits of
AN4 AD conversion
result
Overrun flag
0:No generate
1: Generate
AD conversion
result store
flag
1: Stored
AD Conversion Result Register 4 High
7 6 5 4 3 2 1 0
bit Symbol ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function Store Upper 8 bits of AN4 AD conversion result
AD Conversion Result Register 5 Low
7 6 5 4 3 2 1 0
bit Symbol ADR51 ADR50 OVR5 ADR5RF
Read/Write R R R
After reset 0 0 0 0
Function Store Lower 2 bits of
AN5 AD conversion
result
Overrun flag
0:No generate
1: Generate
AD conversion
result store
flag
1: Stored
AD Conversion Result Register 5 High
7 6 5 4 3 2 1 0
bit Symbol ADR59 ADR58 ADR57 ADR56 ADR55 ADR54 ADR53 ADR52
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function Store Upper 8 bits of AN5 AD conversion result
9 8 76543210
Channel X conversion result
7 6 543210 76543 2 1 0
Figure 3.23.8 AD Conversion Registers
A
DREG4L
(12A8H)
A
DREG4H
(12A9H)
A
DREG5L
(12AAH)
A
DREG5H
(12ABH)
A
DREGxH ADREGxL
• Bits 5 ∼ 2 are always read as “0”.
• Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
• Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.