Filter
Top Products
TMP92CZ26A
92CZ26A-438
Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission))
IDLE
Receive IN token
Confirm Status
• Confirm STATUS register (status)
Generate DATA PID
• Attach DATA0
• Confirm DATASIZE register
Transmit data
OK
OK
OK
Attach CRC
Error transaction
Not receive SOF
Not renewal frame number
loss data
Receive SOF
without transmitting data
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
Invalid
Erro
r
IDLE
Clear X condition (A)
Set FULL to STATUS
Set LOST to FRAME register
Not renew FRAME number
A
ssert SOF
ReceiveSOF
• FRAME noread
• BANK shift
BANK B transaction
• Assert SOF
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register’s BANK A bit
• Set DATASET register’s BANK B bit
(Finish a write in previous frame)
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)
BANK A transaction
• Assert SOF
• Clear transmitting FIFO BANK B in preceding
frame
• Clear DATASET register’s BANK B bit
• Set DATASET register’s BANK A bit
(Finish a write in previous frame)
• Set STATUS to READY
Shift FIFO BANKs
every receive SOF