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TMP92CZ26A
92CZ26A-439
(d-2) Isochronous receiving mode
Isochronous transfer type format in receiving is below transaction format.
• Token: OUT
• Data: DATA0
Control flow
Isochronous transfer type is frame management. And data that is written to
FIFO by OUT token is received to CPU in next frame.
Below are two conditions in FIFO of Isochronous receiving mode
transferring
X. FIFO for storing data that received from host in present frame
(DATASET register bit = 0)
Y. FIFO for storing data for transmitting host in previous frame
(DATASET register bit = 1)
FIFO that is divided into two (packet A and packet B) conditions is whether
X condition or Y condition. Below flow is explained as X Condition (packet A),
Y Condition (packet B) in present frame.
X and Y conditions change one after the other by receiving SOF.
Below is control flow in UDC when receiving OUT token.
All transaction is processed by hardware.
1. Token packet is received and address endpoint number error is confirmed,
and it checks whether conform applicable endpoint transfer mode with
OUT token. If it doesn’t conform, state return to IDLE.
2. Condition of status register is confirmed.
• INVALID condition: State return to IDLE.
3. Data packet is received.
Data is transferred from SIE into the UDC to packet A’s FIFO (X
Condition).
4. After last data was transferred, and compare counted CRC with
transferred CRC. When transfer finish, result is reflected to STATUS.
However, data is stored FIFO, data number that packet A is received is
set to DATASIZE register of packet A.
5. Below is transaction when SOF token from host is received.
• Change the packet A’s FIFO from X Condition to Y Condition.
• Change the packet B from Y Condition to X Condition, and clear data.
Prepare for next transfer.
• Set frame number to frame register.
• Assert SOF and inform that frame is incremented to external.
• DATASET register set packet A bit and it clear packet B bit
arrangement loading in present frame.
• If CRC comparison result agree it, DATAIN is set to STATUS. If
result doesn’t agree, RX_ERR is set to STATUS.
UDC finishes normally by above transaction.
CPU takes back packet A’s data.