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TMP92CZ26A
92CZ26A-94
(5) HDMAMn (DMA Transfer Mode Setting Register)
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.
HDMAMn Register
7 6 5 4 3 2 1 0
bit Symbol DnM4 DnM3 DnM2 DnM1 DnM0
Read/Write R/W
After reset 0 0 0 0 0
Function
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved (Note 2)
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
Transfer mode
[7: 0]
Channel 0
HDMAM0
(090CH)
Channel 1
HDMAM1
(091CH)
Channel 2
HDMAM2
(092CH)
Channel 3
HDMAM3
(093CH)
Channel 4
HDMAM4
(094CH)
Channel 5
HDMAM5
(095CH)
Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented
Figure 3.6.6 HDMAMn Register
HDMAMn