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TMP92CZ26A
92CZ26A-386
3.16.3.8 Setup Received Register
This register informs for the UDC that an application program recognized
INT_SETUP interrupt.
7 6 5 4 3 2 1 0
bit Symbol
D7 D6 D5 D4 D3 D2 D1 D0
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
If this register is accessed by an application program, the UDC release to disabling
access to EP0’s FIFO RAM because the UDC recognized the device request is received.
This is to protect data stored in EP0 in the time from continuous request has been
asserted to an application program recognized INT_SETUP interrupt.
Therefore, write “00H” to this register when the device request in INT_SETUP
routine is recognized.
Note : When EP0_FIFO is accessed register after wrote to this register, the recovery time of 2clock at 12MHz is
needed.
3.16.3.9 Current_Config Register
This register shows the present value that is set by SET_CONFIGURATION and
SET_INTERFACE.
7 6 5 4 3 2 1 0
bit Symbol REMOTEWAKEUP ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0] CONFIG[1] CONFIG[0]
Read/Write R R R R R R R
After reset 0 0 0 0 0 0 0
CONFIG[1:0] (Bit1 to bit0)
00: UNCONFIGURED Set to UNCONFIGURED by the host.
01: CONFIGURED1 Set to CONFIGURED 1 by the host.
10: CONFIGURED2 Set to CONFIGURED 2 by the host.
INTERFACE[1:0] (Bit3 to bit2)
00: INTERFACE0 Set to INTERFACE 0 by the host.
01: INTERFACE1 Set to INTERFACE 1 by the host.
10: INTERFACE2 Set to INTERFACE 2 by the host.
ALTERNATE[1:0] (Bit5 to bit4)
00: ALTERNATE0 Set to ALTERNATE 0 by the host.
01: ALTERNATE1 Set to ALTERNATE 1 by the host.
10: ALTERNATE2 Set to ALTERNATE 2 by the host.
REMOTE WAKEUP (Bit7)
0: Disable Disabled remote wakeup by the host.
1: Enable Enabled remote wakeup by the host.
Note1: Config, INTERFACE and ALTERNATE each support 3 kinds (0,1 and 2).
Note2: If each request is controlled by S/W, this register is not set.
SetupReceived
(07C8H)
Current_Config
(07C9H)