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TMP92CZ26A
92CZ26A-120
Port 4 register
7 6 5 4 3 2 1 0
bit Symbol P47 P46 P45 P44 P43 P42 P41 P40
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Port 4 Function register
7 6 5 4 3 2 1 0
bit Symbol P47F P46F P45F P44F P43F P42F P41F P40F
Read/Write W
After reset
Note2:
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Function
0:Port 1:Address bus (A0 to A7)
Port 4 Drive register
7 6 5 4 3 2 1 0
bit Symbol P47D P46D P45D P44D P43D P42D P41D P40D
Read/Write
R/W
After reset 1 1 1 1 1 1 1 1
Function Input/Output buffer drive register for standby mode
Note1: Read-modify-write is prohibited for P4FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.4 Register for Port1r
P4
(0010H)
P4FC
(0013H)
P4DR
(0084H)