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TMP92CZ26A
92CZ26A-423
Figure 3.16.7 Control Flow in UDC (Bulk transfer type (transmission)/Interrupt transfer type (transmission))
IDLE
Receive IN token
Confirm Handshake answer
• Confirm STATUS register (Status)
• Confirm DATASET register
Generate DATA PID
• Attach DATA0/DATA1
• Confirm Datasize register
Transmit data
OK
OK
OK
Attach CRC
OK
Receive ACK
Wait ACK
to host
Normal finish transaction
• Clear FIFO
• Clear DATASET register
• Renew toggle bit
• Set STATUS to READY
OK
Time out
• Set STATUS to TX_ERR
• Put back addless pointer of FIFO
Bit stuff error
Set STATUS at STALL
ConfirmToken packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
Transmit NAK Transmit STALL
Invalid
Stall
FIFO em
p
t
y
More than MAX
p
a
y
load
Erro
r