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TMP92CZ26A
92CZ26A-41
Table 3.3.7 Output buffer State Table (1/2)
Output Buffer State
In HALT mode (IDLE2/1/STOP)
When the CPU is operating
<PxDR>=1 <PxDR>=0
Port Name
Output Function
Name
During Reset
When Used
as function
Pin
When Used
as Output
port
When Used
as function
Pin
When Used
as Output
port
When Used
as function
Pin
When Used
as Output
port
D0-7 D0-7 OFF − − −
P10-17 D8-15
16bit Start ON
Boot Start OFF
ON upon
external write
ON
OFF
ON
P40-P47 A0-A7
P50-P57 A8-A15
ON
P60-67 A16-A23
16bit Start ON
Boot Start OFF
P70 RD ON
P71 WRLL ,NDRE
P72
WRLU
,
NDWE
P73 EA24
P74 EA25
P75 R/ W
ON ON
OFF
P76 −
OFF
− − −
P80
0CS
P81
1CS
,
SDCS
P82
2CS
,
CSZA
,
SDCS
P83
3CS
,
CSXA
P84
CSZB
P85
CSZC
P86
CSZD
,
CE0ND
P87 CSXB , CE1ND
ON
P90 TXD0
ON ON OFF
P91 − − − −
P92 SCLK0
OFF
ON ON
OFF
P96 PX
P97 PY
ON
−
ON
−
OFF
−
PC0-PC3 − − − −
PC4 EA26
PC5 EA27
PC6 EA28
PC7 KO8
PF0 I2S0CKO
PF1 I2S0DO
PF2 I2S0WS
PF3 I2S1CKO
PF4 I2S1DO
PF5 I2S1WS
OFF
PF7 SDCLK ON
ON ON OFF
PG2 MX
PG3 MY
OFF − − −
PJ0
SDRAS
,
SRLLB
PJ1
SDCAS
,
SRLUB
PJ2
SDWE
,
SRWR
PJ3 SDLLDQM
PJ4 SDLUDQM
ON
PJ5 NDALE
PJ6 NDCLE
OFF
PJ7 SDCKE
PK0 LCP0
PK1 LLOAD
PK2 LFR
PK3 LVSYNC
PK4 LHSYNC
PK5 LGOE0
PK6 LGOE1
PK7 LGOE2
PL0-PL7 LD0-LD7
ON
ON
ON
ON
ON
OFF
OFF