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TMP92CZ26A
92CZ26A-429
Figure 3.16.9 Control Flow in UDC (Setup stage)
IDLE
Receive SETUP token
Confirm Status
• Confirmation STATUS register (Status)
Confirm DATA PID
• DATA0
• Time out
OK
OK
OK
OK
Transmit ACK
Normal finish transaction
• Set DATASET register
• Assert INT_SETUP and request flag
• According to stage flow, prepare for next stage
• Set STATUS to DATAIN
• Set toggle bit to 1
OK
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
Invalid
Except DATA0 PID
Time out
Erro
r
Error transaction
• Set STATUS to RX_ERR
• Put back FIFO address point
Receive data
• Error
• Confirm receving data
number
Erro
r
, more than payload data comunication