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TMP92CZ26A
92CZ26A-734
(15) 16-bit timer (1/2)
Symbol Name
Address 7 6 5 4 3 2 1 0
TB0RDE − I2TB0 TB0PRUN TB0RUN
R/W R/W R/W R/W R/W
0 0 0 0 0
TMRB0
prescaler
Up
counter
(UC10)
TB0RUN
TMRB0
RUN
register
1180H
Double
buffer
0: disable
1: enable
Always
write “0”.
IDLE2
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
− − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0
R/W W* R/W
0 0 1 0 0 0 0 0
TB0MOD
TMRB0
MODE
register
1182H
(Prohibit
RMW)
Always write “00”. Software
capture
control
0: Execute
1: Undefined
Capture timing
00: Disable
INT6 occurs at rising
edge
01: TB0IN0 ↑
INT6 occurs at rising
edge
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at falling
edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
Control
Up
counter
0:Clear
Disable
1:Clear
Enable
TMRB1 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
− − TB0CT1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0
W* R/W W*
1 1 0 0 0 0 1 1
TB1FF0 inversion trigger
0: Disable trigger
1: Enable trigger
TB0FFCR
TMRB0
Flip-Flop
control
register
1183H
(Prohibit
RMW)
Always write “11”.
*Always read as “11”.
When
capture
UC10 to
TB0CP1H/L
When
capture
UC10 to
TB0CP0H/L
When UC10
matches
with
TB0RG1H/L
When UC10
matches
with
TB0RG0H/L
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
*
Always read as “11”.
−
W
TB0RG0L
16 bit timer
register 0
low
1188H
(Prohibit
RMW)
0
−
W
TB0RG0H
16 bit timer
register 0
high
1189H
(Prohibit
RMW)
0
−
W
TB0RG1L
16 bit timer
register low
118AH
(Prohibit
RMW)
0
−
W
TB0RG1H
16 bit timer
register 1
high
118BH
(Prohibit
RMW)
0
−
R
TB0CP0L
Capture
register 0
low
118CH
Undefined
−
R
TB0CP0H
Capture
register 0
high
118DH
Undefined
−
R
TB0CP1L
Capture
register 1
low
118EH
Undefined
−
R
TB0CP1H
Capture
register 1
high
118FH
Undefined