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TMP92CZ26A
92CZ26A-173
Port W register
7 6 5 4 3 2 1 0
bit Symbol PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
Read/Write R/W
After reset
Data from external port (Output latch register is cleared to “0”)
Port W control register
7 6 5 4 3 2 1 0
bit Symbol PW7C PW6C PW5C PW4C PW3C PW2C PW1C PW0C
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function 0: Input 1: Output
Port W function register
7 6 5 4 3 2 1 0
bit Symbol PW7F PW6F PW5F PW4F PW3F PW2F PW1F PW0F
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function 0: Port 1: Reserved
Port W drive register
7 6 5 4 3 2 1 0
bit Symbol PW7D PW6D PW5D PW4D PW3D PW2D PW1D PW0D
Read/Write R/W
After reset 1 1 1 1 1 1 1 1
Function Input/Output buffer drive register for standby mode
Note1: Read-Modify-Write is prohibited for the registers PWCR, PWFC.
Figure 3.7.62 Register for Port W
PW
(00ACH)
PWFC
(00AFH)
PWCR
(00AEH)
PWDR
(009EH)