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TMP92CZ26A
92CZ26A-232
(b) Self Refresh
The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”.
Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM
is refreshed internally without the need to issue the Auto Refresh command.
Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is
exited. Note that the Auto Refresh function is also disabled at this time.
Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state.
Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or other
instructions between the instruction to set SDCMM<SCMM2:0> to “101” and the HALT instruction.
Figure3.10.7 Self Refresh Cycle Timing
SDCLK
SDCKE
SDLUDQM
SDLLDQM
Self Refresh Entry
Auto Refresh Mode
Set
Self Refresh Exit
SDCS
SDRAS
SDCAS
SDWE