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TMP92CZ26A
92CZ26A-504
The following shows how written data is output under various conditions.
When I2SnCTL<WLVLn> = 0
When I2SnCTL<WLVLn> = 1
Note: In case of using monaural setting, and change right / left: I2SnCTL<WLVLn>, data output order change
off 1'st data and 2'nd data.
I2SnBUF register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB-first 16 bits
LSB-first 16 bits
Output order
MSB-first 8 bits
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
2’nd Data
1’st Data
4’th Data
3’rd Data
2’nd Data
1’st Data
1’st Data
2’nd Data
1’st Data 2’nd Data
3’rd Data 4’th Data
I2SnBUF register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB-first 16 bits
LSB-first 16 bits
Output order
MSB-first 8 bits
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
2’nd Data
1’st Data
4’th Data 3’rd Data
2’nd Data 1’st Data
1’st Data
2’nd Data
1’st Data 2’nd Data
3’rd Data
4’th Data