Filter
Top Products
TMP92CZ26A
92CZ26A-422
(a-1) Transmission bulk mode
Below is transaction format of bulk transfer during transmitting.
• Token: IN
• Data: DATA0/DATA1, NAK, STALL
• Handshake: ACK
Control flow
Below is control-flow when UDC receive IN token.
1. Token packet is received and address endpoint number error is confirmed, and it
checks whether conform applicable endpoint transfer mode with IN token. If it
doesn’t conform, state return to IDLE.
2. Condition of EPx_STATUS register is confirmed.
• INVALI condition: State return to IDLE.
• STAL condition: Stall handshake is returned and state return to IDLE.
FIFO condition is confirmed, if data number of 1 packet is not prepared, NAK
handshake is returned, and state return to IDLE.
If data number of 1 packet is prepared to FIFO, it shifts to 3.
3. Data packet is generated.
Data packet generated by using toggle bit register in UDC.
Next, it transfers data from FIFO of internal UDC to SIE, and data packet is
generated. At this point, it confirms transferred data number. And if there is more
than max payload size of each endpoint, bit stuff error is generated, and finish
transfer. And STATUS becomes to STALL.
4. CRC bit (counted transfer data of FIFO from first to last) is attached to last.
5. When ACK handshake from host is received,
• Clear FIFO.
• Clear DATASET register.
• Renew toggle bit, and prepare for next.
• Set STATUS to READY.
UDC finishes normally. FIFO can be received next data.
If it is time out without receiving ACK from host,
• Set STATUS to TX_ERR.
• Put back addles pointer of FIFO.
Execute above setting. And wait next retry keeping FIFO data.
This flow is
Figure 3.16.7.