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TMP92CZ26A
92CZ26A-163
Port R register
7 6 5 4 3 2 1 0
bit Symbol PR3 PR2 PR1 PR0
Read/Write R/W
After reset
Data from external port
(Output latch register is cleared to “0”)
Port R control register
7 6 5 4 3 2 1 0
bit Symbol PR3C PR2C PR1C PR0C
Read/Write W
After reset 0 0 0 0
Function 0: Input, 1: Output
Port R function register
7 6 5 4 3 2 1 0
bit Symbol PR3F PR2F PR1F PR0F
Read/Write W
After reset 0 0 0 0
Function
0: Port
1: SPCLK
0: Port
1:
SPCS
0: Port
1: SPDO
0: Port
1: SPDI
Port R drive register
7 6 5 4 3 2 1 0
bit Symbol PR3D PR2D PR1D PR0D
Read/Write R/W
After reset 1 1 1 1
Function
Input/Output buffer drive register
for standby mode
Note: Read-Modify-Write is prohibited for the registers PRCR, PRFC.
Figure 3.7.51 Register for Port R
PR
(0064H)
PRFC
(0067H)
PRDR
(0099H)
PRCR
(0066H)
<PR0C>
<PR0F>
0 1
0 Input port Output port
1 SPDI input (Reserved)
PR0 setting
<PR1C>
<PR1F>
0 1
0 Input port Output port
1 (Reserved) SPDO output
PR1 setting
<PR2C>
<PR2F>
0 1
0 Input port Output port
1 (Reserved) SPCS Output
PR2 setting
<PR3C>
<PR3F>
0 1
0 Input port Output port
1
(Reserved) SPCLK
output
PR3setting