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TMP92CZ26A
92CZ26A-28
3.3.4 Clock doubler (PLL)
PLL0 outputs the f
PLL
clock signal, which is 12 or 16 times as fast as f
OSCH
. That is, the
low-speed frequency oscillator can be used as external oscillator, even though the internal
clock is high-frequency.
Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is
needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time
and it is measured by 12-stage binary counter. Lock-up time is about 0.41ms at f
OSCH
=
10MHz.
PLL (PLL1) which is special for USB is build in. Lock-up time is about 0.82ms at f
OSCH
=
10MHz measured by 13-stage binary counter.
Note1: Input frequency limitation for PLL
The limitation of input frequency (High frequency oscillation) for PLL is following.
f
OSCH
= X to X MHz (Vcc = 1.4 to 1.6V)
Note2: PLLCR0<LUPFG>
The logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
Be careful to judge an end of lock-up time.
Note3: PLLCR1<PLL0>, PLLCR1<PLL1>
It’s prohibited to turn ON both PLL0 and PLL1 simultaneously.
If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL.
Figure 3.3.7 shows the frequency of f
SYS
when using PLL and clock gear at f
OSCH
=10MHz.
Figure 3.3.7 The frequency of f
SYS
at f
OSH
=10MHz
Frequency of f
SYS
f
OSH
f
PLL
fc fc/2 fc/4 fc/8 fc/16
f
OSH
10MHz 10MHz 5MHz 2.5MHz 1.25MHz 625KHz
×12 120MHz 60MHz 30MHz 15MHz 7.5MHz 3.75MHz
10MHz
×16 160MHz 80MHz 40MHz 20MHz 10MHz 5MHz