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TMP92CZ26A
92CZ26A-78
(1) Interrupt priority setting registers
Symbol Name Address 7 6 5 4 3 2 1 0
− INT0
− − − − I0C I0M2 I0M1 I0M0
R R/W R R/W
INTE0
INT0
enable
F0H
Always write “0”.
0 0 0 0
INT2 INT1
I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0
R R/W R R/W
INTE12
INT1 & INT2
enable
D0H
0 0 0 0 0 0 0 0
INT4 INT3
I4C I4M2 I4M1 I4M0 I3C I3M2 I3M1 I3M0
R R/W R R/W
INTE34
INT3 & INT4
enable
D1H
0 0 0 0 0 0 0 0
INT6 INT5
I6C I6M2 I6M1 I6M0 I5C I5M2 I5M1 I5M0
R R/W R R/W
INTE56
INT5 & INT6
enable
D2H
0 0 0 0 0 0 0 0
− INT7
− − − − I7C I7M2 I7M1 I7M0
R R/W R R/W
INTE7
INT7
enable
D3H
Always write “0”.
0 0 0 0
INTTA1 (TMRA1) INTTA0 (TMRA0)
ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0
R R/W R R/W
INTETA01
INTTA0 &
INTTA1
enable
D4H
0 0 0 0 0 0 0 0
INTTA3 (TMRA3) INTTA2 (TMRA2)
ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0
R R/W R R/W
INTETA23
INTTA2 &
INTTA3
enable
D5H
0 0 0 0 0 0 0 0
INTTA5 (TMRA5) INTTA4 (TMRA4)
ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0
R R/W R R/W
INTETA45
INTTA4 &
INTTA5
enable
D6H
0 0 0 0 0 0 0 0
INTTA7 (TMRA7) INTTA6 (TMRA6)
ITA7C ITA7M2 ITA7M1 ITA7M0 ITA6C ITA6M2 ITA6M1 ITA6M0
R R/W R R/W
INTETA67
INTTA6 &
INTTA7
enable
D7H
0 0 0 0 0 0 0 0
lxxM2 lxxM1 lxxM0 Function (Write)
0 0 0 Disables interrupt requests
0 0 1 Sets interrupt priority level to 1
0 1 0 Sets interrupt priority level to 2
0 1 1 Sets interrupt priority level to 3
1 0 0 Sets interrupt priority level to 4
1 0 1 Sets interrupt priority level to 5
1 1 0 Sets interrupt priority level to 6
1 1 1 Disables interrupt requests
Interrupt request flag