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TMP92CZ26A
92CZ26A-301
(6) Comparators (CP10, CP11)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter
UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect
a match. If a match is detected, the comparator generates an interrupt (INTTB00 or
INTTB01 respectively).
(7) Timer flip-flops (TB0FF0, TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C0T1, TB0E1T1, TB0E0T1>.
After a reset the value of TB0FF0 is undefined. If “00” is written to TB0FFCR
<TB0FF0C1:0> or <TB0FF1C1:0>, TB0FF0 will be inverted. If “01” is written to the
capture registers, the value of TB0FF0 will be set to “1”. If “10” is written to the
capture registers, the value of TB0FF0 will be set to “0”.
Note: If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs
simultaneously, the resultant operation varies depending on the situation, as shown below.
• If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
flip-flop will be inverted only once.
• If an inversion by the match-detect siganl and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the flip-flop will be set to 1.
• If an inversion by the match-detect signal and an attmept to cleare the flip-flop to 0 via the register
occur simultanerously, the flip-flop will be cleared to 0.
If an inversion by match-detect signal and inversion disable setting occur
simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore,
if changing inversion control (inversion enable/disable), stop timer operation
beforehand.
The values of TB0FF0 and TB0FF1 can be output via the timer output pins
TB0OUT0 (which is shared with PP6) and TB0OUT1 (which is shared with PP7).
Timer output should be specified using the port P function register.