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TMP92CZ26A
92CZ26A-131
Figure 3.7.15 P91, 92
Figure 3.7.16 Port 96,97
Internal data bus
Selector
A
B
S
Selector
A
B
S
P91(RXD0)
P92(SCLK0,
0CTS
)
SCLK0 output
P9 read
Direction
control
(
on bit basis
)
P9CRwrite
Function
control
(
on bit basis
)
S
Output latch
P9 write
Reset
P9FCwrite
RXD0 input
SCLK0 input
0CTS
input
TSICR0<PXEN>
<PYEN>
IIMC<I4EDGE>
P96 (INT4,PX)
P97 (PY)
P9 read
Function
control
Reset
P9FC write
INT4
Rising/Falling
edge-ditection
TSICR0<TSI7>
TSICR0<PXEN>
TSICR0<TSI7>
Selector
De-bounce
Circuit
A
S
TSICR1<DBC7>
Only for P96
A
VCC
Switch for TSI
typ.10
Ω
Pull-down resistor
typ.50K
Ω
B
TSICR0<TWIEN , TSI7>
Internal data bus