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TMP92CZ26A
92CZ26A-92
(3) HDMACAn (DMA Transfer Count A Setting Register)
The HDMACAn register is used to set the number of times a DMA transfer is to be
performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536
transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even
when the transfer count A is updated by DMA execution, HDMACAn is not updated.
HDMACA0 to HDMACA5 have the same configuration.
HDMACAn Register
7 6 5 4 3 2 1 0
bit Symbol DnCA7 DnCA6 DnCA5 DnCA4 DnCA3 DnCA2 DnCA1 DnCA0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Transfer count A [7:0] for DMAn
15 14 13 12 11 10 9 8
bit Symbol DnCA15 DnCA14 DnCA13 DnCA12 DnCA11 DnCA10 DnCA9 DnCA8
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Transfer count A [15:8] for DMAn
Transfer count A
[15: 8]
Transfer count A
[7: 0]
Channel 0
(0909H)
HDMACA0
(0908H)
Channel 1
(0919H)
HDMACA1
(0918H)
Channel 2
(0929H)
HDMACA2
(0928H)
Channel 3
(0939H)
HDMACA3
(0938H)
Channel 4
(0949H)
HDMACA4
(0948H)
Channel 5
(0959H)
HDMACA5
(0958H)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.4 HDMACAn Register
HDMACAn