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TMP92CZ26A
92CZ26A-693
(3) Memory controller (1/4)
Symbol Name
Address 7 6 5 4 3 2 1 0
B0WW3 B0WW2 B0WW1 B0WW0 B0WR3 B0WR2 B0WR1 B0WR0
R/W
0 0 1 0 0 0 1 0
Write waits Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 wait
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0011: 6 states +
WAIT
pin input mode 0011: 6 states +
WAIT
pin input mode
B0CSL
BLOCK0
CS/WAIT
control
register
low
0140H
(Prohibit
RMW)
Others: Reserved Others: Reserved
B0E B0REC B0OM1 B0OM0 B0BUS1 B0BUS0
R/W
R/W
0 0 0 0 0 0
B0CSH
BLOCK0
CS/WAIT
control
register
high
0141H
(Prohibit
RMW)
CS select
0: Disable
1: Enable
Dummy
cycle
0:No insert
1: Insert
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B1WW3 B1WW2 B1WW1 B1WW0 B1WR3 B1WR2 B1WR1 B1WR0
R/W
0 0 1 0 0 0 1 0
Write waits Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0011: 6 states +
WAIT
pin input mode 0011: 6 states +
WAIT
pin input mode
B1CSL
BLOCK1
CS/WAIT
control
register
low
0144H
(Prohibit
RMW)
Others: Reserved Others: Reserved
B1E B1REC B1OM1 B1OM0 B1BUS1 B1BUS0
R/W
R/W
0 0 0 0 0 0
B1CSH
BLOCK1
CS/WAIT
control
register
high
0145H
(Prohibit
RMW)
CS select
0: Disable
1: Enable
Dummy
cycle
0:No
insert
1: Insert
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B2WW3 B2WW2 B2WW1 B2WW0 B2WR3 B2WR2 B2WR1 B2WR0
R/W
0 0 1 0 0 0 1 0
Write waits Read waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0011: 6 states +
WAIT
pin input mode 0011: 6 states +
WAIT
pin input mode
B2CSL
BLOCK2
CS/WAIT
control
register
low
0148H
(Prohibit
RMW)
Others: Reserved Others: Reserved
B2E B2M B2REC B2OM1 B2OM0 B2BUS1 B2BUS0
R/W
R/W
1 0 0 0 0 0 1
B2CSH
BLOCK2
CS/WAIT
control
register
high
0149H
(Prohibit
RMW)
CS select
0: Disable
1: Enable
0: 16 MB
1: Sets
area
Dummy
cycle
0:No
insert
1: Insert
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set