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TMP92CZ26A
92CZ26A-192
(5) Recovery (Data hold) cycle control
Some memory have an AC specification about data hold time from
CE
or
OE
for read
cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can
be inserted after CSm-block access cycle by setting “1” to BmCSH<BmREC> register.
This 1-dummy cycle is inserted when the next cycle is for another CS-block.
BnCSH<BnREC>
0 No dummy cycle is inserted (Default).
1 Dummy cycle is inserted.
When not inserting a dummy cycle (0 waits)
When inserting a dummy cycle (0 waits)
SDCLK
A23 to A0
CSm
CSn
RD
SDCLK
A23 to A0
CSm
CSn
RD
Dumm
y