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TMP92CZ26A
92CZ26A-10
Table 2.2.1 Pin names and functions (3/6)
Pin name
Number of
Pins
I/O Functions
PF0
I2S0CKO
1
I/O
Output
Port F0: I/O port.
Outputs clock of I2S0.
PF1
I2S0DO
1
I/O
Output
Port F1: I/O port.
Outputs data of I2S0.
PF2
I2S0WS
1
I/O
Output
Port F2: I/O port.
Outputs word select signal of I2S0.
PF3
I2S0WS
1
I/O
Output
Port F3: I/O port.
Outputs clock of I2S1.
PF4
I2S1CKO
1
I/O
Output
Port F4: I/O port.
Outputs data of I2S1.
PF5
I2S1WS
1
I/O
Output
Port F5: I/O port.
Outputs word select signal of I2S1.
PF7
SDCLK
1
Output
Output
Port F7: Output port.
Clock for SDRAM.
PG0 to PG1
AN0 to AN1
2
Input
Input
Port G0 to G1: Input port.
Analog input pin 0 to 1 : Input pin of A/D converter.
PG2
AN2
MX
1
Input
Input
Output
Port G2: Input port.
Analog input pin 2 : Input pin of A/D converter.
X-Minus : Pin connected to X- pin for Touch Screen I/F.
PG3
AN3
MY
ADTRG
1
Input
Input
Output
Input
Port G3: Input port.
Analog input pin 3 : Input pin of A/D converter.
Y-Minus : Pin connected to Y- pin for Touch Screen I/F.
A/D Trigger : Request signal of A/D start.
PG4 to PG5
AN4 to AN5
2
Input
Input
Port G4 to G5: Input port.
Analog input pin 4 to 5 : Input pin of A/D converter.
PJ0
SDRAS
SRLLB
1
Output
Output
Output
Port J0: Output port.
Outputs strobe signal of SDRAM row address.
Data enable signal for D0 to D7 of SRAM.
PJ1
SDCAS
SRLUB
1
Output
Output
Output
Port J1: Output port.
Outputs strobe signal of SDRAM column address.
Data enable signal for D8 to D15 of SRAM.
PJ2
SDWE
SRWR
1
Output
Output
Output
Port J2: Output port.
Outputs write enable signal of SDRAM.
Write enable of SRAM: Outputs strobe signal to write data.
PJ3
SDLLDQM
1
Output
Output
Port J3: Output port.
Data enable signal for D0 to D7 of SDRAM.
PJ4
SDLUDQM
1
Output
Output
Port J4: Output port.
Data enable signal for D8 to D15 of SDRAM.
PJ5
NDALE
1
I/O
Output
Port J5: I/O port.
Address latch enable signal of NAND Flash.
PJ6
NDCLE
1
I/O
Output
Port J6: I/O port.
Command latch enable signal of NAND Flash.
PJ7
SDCKE
1
Output
Output
Port J7: Output port.
Clock enable signal of SDRAM.