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TMP92CZ26A
92CZ26A-698
(5) SDRAM controller
Symbol Name
Address 7 6 5 4 3 2 1 0
SRDS − SMUXW1 SMUXW0 SPRE SMAC
R/W R/W
1 0 0 0 0 0
SDACR
SDRAM
access
control
register
0250H
Read
data shift
function
0: Disable
1: Enable
Always
write “0”
Address multiplex
type
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
Read/Write
commands
0: Without
auto pre-
charge
1: With auto
precharge
SDRAM
controller
0: Disable
1: Enable
STMRD STWR STRP STRCD STRC2 STRC1 STRC0
R/W
1 1 1 1 1 0 0
SDCISR
SDRAM
Command
Interval
Setting
Register
0251H
TMRD
0: 1 CLK
1: 2 CLK
TWR
0: 1 CLK
1: 2 CLK
TRP
0: 1 CLK
1: 2 CLK
TRCD
0: 1 CLK
1: 2 CLK
TRC
000: 1 CLK 100: 5 CLK
001: 2 CLK 101: 6 CLK
010: 3 CLK 110: 7 CLK
011: 4 CLK 111: 8 CLK
− SSAE SRS2 SRS1 SRS0 SRC
R/W R/W
0 1 0 0 0 0
SDRCR
SDRAM
refresh
control
register
0252H
Always
write “0”
Self
Refresh
auto
exit
function
0:Disable
1:Enable
Refresh interval
000: 47 states 100: 468 states
001: 78 states 101: 624 states
010: 156 states 110: 936 states
011: 312 states 111: 1248 states
Auto
Refresh
0:Disable
1:Enable
SCMM2 SCMM1 SCMM0
R/W
0 0 0
SDCMM
SDRAM
command
register
0253H
Command issue
000: Don’t care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
SDBL5 SDBL4 SDBL3 SDBL2 SDBL1 SDBL0
0 0 0 0 0 0
For
HDMA5
For
HDMA4
For
HDMA3
For
HDMA2
For
HDMA1
For
HDMA0
SDBLS
SDRAM
HDRAM
burst length
register
0254H
HDMA burst length
0:1 Word Read / Single Write
1:Full Page Read / Burst Write