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TMP92CZ26A
92CZ26A-91
(2) HDMADn (DMA Transfer Destination Address Setting Register)
The HDMADn register is used to set the DMA transfer destination address. When the
destination address is updated by DMA execution, HDMADn is also updated.
HDMAD0 to HDMAD5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
HDMADn Register
7 6 5 4 3 2 1 0
bit Symbol DnDA7 DnDA6 DnDA5 DnDA4 DnDA3 DnDA2 DnDA1 DnDA0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Destination address [7:0] for DMAn
15 14 13 12 11 10 9 8
bit Symbol DnDA15 DnDA14 DnDA13 DnDA12 DnDA11 DnDA10 DnDA9 DnDA8
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function
Destination address [15:8] for DMAn
23 22 21 20 19 18 17 16
bit Symbol DnDA23 DnDA22 DnDA21 DnDA20 DnDA19 DnDA18 DnDA17 DnDA16
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Destination address [23:16] for DMAn
Destination
address
[23: 16]
Destination
address
[15: 8]
Destination
address
[7: 0]
Channel 0
(0906H)
(0905H)
HDMAD0
(0904H)
Channel 1
(0916H)
(0915H)
HDMAD1
(0914H)
Channel 2
(0926H)
(0925H)
HDMAD2
(0924H)
Channel 3
(0936H)
(0935H)
HDMAD3
(0934H)
Channel 4
(0946H)
(0945H)
HDMAD4
(0944H)
Channel 5
(0956H)
(0955H)
HDMAD5
(0954H)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.3 HDMADn Register
HDMADn