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TMP92CZ26A
92CZ26A-327
(12) Timing generation
a. In UART Mode
Receiving
Mode
9-Bit
(Note)
8-Bit + Parity
(Note)
8-Bit, 7-Bit + Parity, 7-Bit
Interrupt timing Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Framing error timing Center of stop bit Center of stop bit Center of stop bit
Parity error timing
Center of last bit
(parity bit)
Center of stop bit
Overrun error timing Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
Transmitting
Mode
9-Bit 8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit
Interrupt timing Just before stop bit is
transmitted
Just before stop bit is
transmitted
Just before stop bit is
transmitted
b. I/O interface
SCLK Output Mode Immediately after last bit. (See Figure 3.14.13.) Transmission
Interrupt
timing
SCLK Input Mode Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See
Figure 3.14.14.)
SCLK Output Mode Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See
Figure 3.14.15.)
Receiving
Interrupt
timing
SCLK Input Mode Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See
Figure 3.14.16.)