Toshiba H1 Series Network Card User Manual


 
TMP92CZ26A
92CZ26A-489
(3) Interrupt
In INTC (interrupt controller), interrupt is divided roughly into 2 kinds; transmit interrupt
(INTSPITX) and receive interrupt (INTSPIRX). Besides in this SPI circuit, there are 4 kinds of
interrupts; 2 transmit interrupts 2 receive interrupts.
Transmit interrupt
TEMP (Empty interrupt of transmit FIFO) and TEND (End interrupt of transmit).
As for TEMP interrupt, the timing of generation differs according to transmit mode;
UNIT/sequential.
If transmit is sequencial, writing the data to transmit FIFO every 16 bytes is always needed. If
writing other than 16 bytes, TEMP interrupt does not generate normally.
UNIT transmit mode
TEMP interrupt generates when the data is shift from transmit data register (SPITD) to
transmit buffer since transmit FIFO is invalid.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
Sequential transmit mode
TEMP interrupt generates from 2 phenomenon. One is when the space of FIFO becomes 16
bytes size and the other 32 bytes size.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
Receive interrupt
RFUL (Receive FIFO interrupt) and REND (Receive finish interrupt).
As for RFUL interrupt, the timing of generation differs according to receive mode;
UNIT/sequential.
If transmit is sequencial, reading the data from receive FIFO every 16 bytes is always needed.
If reading other than 16 bytes, RFUL interrupt does not generate normally.
UNIT receive
RFUL interrupt generates the same timing as REND since the receive FIFO becomes invalid.
RFUL and REND interrupt generate when the data is shifted from receive buffer to receive data
register (SPIRD).
Sequential receive
RFUL interrupt generates from 2 phenomenon. One is when 16 bytes size of data is loaded to
receive FIFO and the other 32 bytes size of data.
REND interrupt generates when the receive FIFO becomes full (32bytes).