Filter
Top Products
TMP92CZ26A
92CZ26A-517
3.19.3 Description of Operation
3.19.3.1 Outline
After the required settings such as the operation mode, display data memory address,
color mode, and LCD size are specified, the start register is set to start the LCDC
operation.
The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC
reads data of the display size from the display RAM, stores the data in the FIFO
buffer in the LCDC, and then returns the bus to the CPU.
The display data in the FIFO buffer is transferred to the LCD driver via a dedicated
bus (LD pin). At this time, control pins (such as LCP0) that are connected to the LCD
driver also output specified waveforms in synchronization with the transfer of display
data.
Note: While display RAM data is being read, the CPU operation is halted by the internal BUSREQ signal.
Therefore, the CPU stop time must be taken into account in programming.
External SDRAM, SRAM, or internal RAM (288 Kbytes) can be used as the display
RAM. Since the internal RAM allows very fast accesses (32-bit bus, 2-1-1-1 read/write),
it enables data transfer to the LCD driver (DMA operation) with the minimum CPU
stop time. Using the internal RAM also greatly reduces power consumption during
LCD display.
3.19.3.2 Display Memory Mapping
Since the number of bits needed to display one pixel varies even for the same display
size depending on the selected color mode, the required display RAM size also varies
with each color mode. (The color mode can be selected from a range of monochrome to
16777216 colors.)
In monochrome mode, one pixel of display data corresponds to one bit of display RAM
data. Likewise, the number of display RAM data used for displaying one pixel in each
color mode is as follows:
4-grayscale 1 pixel = 2 bits
16-grayscale 1 pixel = 4 bits
64-grayscale 1 pixel = 6 bits
STN 256-color 1 pixel = 8 bits
STN 4096-color 1 pixel = 12 bits
STN 65536-color 1 pixel = 16 bits
STN 256K-color 1 pixel = 16 bits (not 18 bits)
STN 16M-color 1 pixel = 24 bits
For example, a 320-segment x 240-common display in 4-grayscale mode requires
19200 bytes of display RAM space (320 × 240 × 2 = 152600 bits = 19200 bytes).
For details, refer to “Memory Map Image and Data Output in Each Display Mode”
later in this chapter.