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TMP92CZ26A
92CZ26A-430
(c-2) Data stage
Data stage is configured by one or plural transaction base on toggle sequence.
Transaction is same with format transmission or receiving bulk transaction.
However, below is difference.
• Toggle bit start from “1” by SETUP stage.
• It judges whether right or not by comparing IN and OUT token with
direction bit of device request. If token that direction is reverse was
received, it is recognized as status stage.
• INT_ENDPOINT0 interrupt is asserted.
(c-3) Status stage
Status stage is configured 0-data-length packet with DATA1’s PID and
handshake behinds IN or OUT token. It uses transaction that direction different
with preceding stage.
Combination is below.
• Control read transfer type: OUT
• Control write transfer type: IN
• Control write transfer type (not dataphase): IN
UDC processes status stage base of control flow in control transfer type. At this
point, CPU must write “0” to EP0 bit of EOP register in last transaction for status
stage finish normally.
Below is detail of status stage.
(c-3-1) IN status stage
Below is IN status stage transaction format.
• Token: IN
• Data: DATA1 (0 data length), NAK, STALL
• Handshake: ACK
Control flow
Below is transaction flow of IN status stage in UDC.
1. Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.
2. STATUS register state is confirmed.
• INVALID condition: State return to IDLE.
• STALL condition: Stall handshake is returned and state return
to IDLE.
It confirm whether EOP register is accessed or not by external. If it
is not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.
3. If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are transmitted.