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TMP92CZ26A
92CZ26A-96
3.6.3 DMAC Operation Description
(1) Overall flowchart
Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is
requested.
Figure 3.6.9 Overall Flowchart
Interrupt specified by
DMA start vector?
Yes
No
Bus ACK?
No
Yes
HDMASn read
HDMADn write
Timer match?
No
Yes
HDMACAn -1=0?
No
Yes
Bus REQ deassert
Internal timer start
HDMACBn -1=0?
Yes
No
INTDMAn assert
END
Interrupt request F/F clear
& bus REQ assert
To general-purpose interrupt or
micro DMA processing flow
Interrupt (DMA) request