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TMP92CZ26A
92CZ26A-93
(4) HDMACBn (DMA Transfer Count B Setting Register)
The HDMACBn register is used to set the number of times a DMA request is to be made.
HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request,
FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated
by DMA execution, HDMACBn is also updated.
HDMACB0 to HDMACB5 have the same configuration.
HDMACBn Register
7 6 5 4 3 2 1 0
bit Symbol DnCB7 DnCB6 DnCB5 DnCB4 DnCB3 DnCB2 DnCB1 DnCB0
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Transfer count B [7:0] for DMAn
15 14 13 12 11 10 9 8
bit Symbol DnCB15 DnCB14 DnCB13 DnCB12 DnCB11 DnCB10 DnCB9 DnCB8
Read/Write R/W
After reset 0 0 0 0 0 0 0 0
Function Transfer count B [15:8] for DMAn
Transfer count B
[15: 8]
Transfer count B
[7: 0]
Channel 0
(090BH)
HDMACB0
(090AH)
Channel 1
(091BH)
HDMACB1
(091AH)
Channel 2
(092BH)
HDMACB2
(092AH)
Channel 3
(093BH)
HDMACB3
(093AH)
Channel 4
(094BH)
HDMACB4
(094AH)
Channel 5
(095BH)
HDMACB5
(095AH)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.5 HDMACBn Register
HDMACBn