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TMP92CZ26A
92CZ26A-533
The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can
be set in a range of 0 to 1024 pulses of the LCP0 clock.
The actual enable width is determined depending on the LCDLDDLY<PDT> setting,
as shown below.
Enable width = <LDW9:0> + 1 (when <PDT> = 1, <LDW9:0>=0 is prohibited)
Enable width = <LDW9:0> (when <PDT> = 0)
LCDLDW Register
7 6 5 4 3 2 1 0
bit Symbol LDW7 LDW6 LDW5 LDW4 LDW3 LDW2 LDW1 LDW0
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function LLOAD width (bits 7-0)
7 6 5 4 3 2 1 0
bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8) LGOE0
width
(bit 8)
LLOAD width (bits 9-8) LHSYNC
width
(bit 8)
When LCDCTL0<LCP0OC>=1, the enable width of the LLOAD signal is shown
below.
LCDLDW
(
0295H
)
LCDHWB8
(
0299H
)
LCP0
LD23-LD0
LCDLDDLY<PDT> = 0
LCDLDDLY<PDT> = 1