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TMP92CZ26A
92CZ26A-234
(7) SDRAM initialization sequence
After reset release, the following sequence of commands can be executed to initialize the
SDRAM.
1. Precharge All command
2. Eight Auto Refresh commands
3. Mode Register Set command
The above commands are issued by setting SDCMM<SCMM2:0> to “001”. While these
commands are issued, the CPU operation (instruction fetch, execution) is halted. Before
executing the initialization sequence, appropriate port settings must be made to enable the
SDRAM control signals and address signals (A0 to A15).
After the initialization sequence is completed, SDCMM<SCMM2:0> is automatically
cleared to “000”.
Figure3.10.9 Initialization Sequence Timing
SDCLK
SDCKE
SDLUDQM
SDLLDQM
A10
A15-A0
Precharge All
Eight Auto Refresh commands
627 227
Auto Refresh Mode Register
Set
Auto Refresh Auto Refresh Auto Refresh Auto Refresh
SDCS
SDRAS
SDCAS
SDWE