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82575EB Gigabit Ethernet Controller — Content
Intel
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82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
10 January 2011
6.6.5.3.2 Advanced Error Reporting Capability............................................................................211
6.6.5.3.3 Device Serial Number ................................................................................................211
7.0 Power Management .............................................................................................................. 215
7.1 Power States .......................................................................................................................... 215
7.2 Auxiliary Power ....................................................................................................................... 216
7.3 Form Factor Power Limits ......................................................................................................... 216
7.4 Power Management Interconnects ............................................................................................. 217
7.4.0.1 PCIe* Link Power Management ......................................................................................217
7.4.0.2 NC-SI Clock Control .....................................................................................................219
7.4.0.3 PHY Power Management ...............................................................................................219
7.4.0.3.1 Link Speed Control....................................................................................................219
7.4.0.3.2 D0a State ................................................................................................................220
7.4.0.3.3 Non-D0a State..........................................................................................................221
7.4.0.3.4 Link Energy Detect....................................................................................................221
7.4.0.3.5 PHY Power-Down State ..............................................................................................221
7.4.0.3.6 SerDes/SGMII Power-Down State................................................................................222
7.4.1 Power States .................................................................................................................... 222
7.4.1.1 Dr State .....................................................................................................................222
7.4.1.1.1 Dr Disable Mode .......................................................................................................222
7.4.1.1.2 Entry to Dr State ......................................................................................................223
7.4.1.2 D0 Uninitialized State ...................................................................................................223
7.4.1.2.1 Entry to D0u State ....................................................................................................223
7.4.1.3 D0 Active State............................................................................................................224
7.4.1.3.1 Entry to D0a State ....................................................................................................224
7.4.1.4 D3 State.....................................................................................................................224
7.4.1.4.1 Entry to D3 State......................................................................................................224
7.4.1.4.2 Master Disable..........................................................................................................225
7.4.1.5 Link-Disconnect ...........................................................................................................225
7.4.2 Power-State Transitions Timing ........................................................................................... 226
7.4.2.1 Power Up (Off to Dup to D0u to D0a)..............................................................................226
7.4.2.2 Transition from D0a to D3 and Back without PE_RST_N.....................................................227
7.4.2.3 Transition from D0a to D3 and Back with PE_RST_N .........................................................228
7.4.2.4 D0a to Dr and Back without Transition to D3 ...................................................................229
7.4.2.5 Timing Requirements....................................................................................................229
7.4.2.6 Timing Guarantees .......................................................................................................230
7.4.3 82575 and SerDes Power-Down State .................................................................................. 230
7.4.3.1 SerDes Power-Down State.............................................................................................230
7.4.3.2 82575 Power-Down State..............................................................................................231
7.5 Wake Up ................................................................................................................................ 231
7.5.1 Advanced Power Management Wakeup................................................................................. 231
7.5.2 PCIe Power Management Wakeup........................................................................................ 232
7.5.3 Wake-Up Packets .............................................................................................................. 233
7.5.3.1 Pre-Defined Filters .......................................................................................................233
7.5.3.1.1 Directed Exact Packet ................................................................................................233
7.5.3.1.2 Directed Multicast Packet ...........................................................................................233
7.5.3.1.3 Broadcast ................................................................................................................234
7.5.3.1.4 Magic Packet* ..........................................................................................................234
7.5.3.1.5 ARP/IPv4 Request Packet ...........................................................................................235
7.5.3.1.6 Directed IPv4 Packet .................................................................................................235
7.5.3.1.7 Directed IPv6 Packet .................................................................................................236
7.5.3.2 Flexible Filter...............................................................................................................236
7.5.3.2.1 IPX Diagnostic Responder Request Packet ....................................................................237
7.5.3.2.2 Directed IPX Packet...................................................................................................237
7.5.3.2.3 IPv6 Neighbor Discovery Filter ....................................................................................238
7.5.3.3 Wake Up Packet Storage ...............................................................................................238
8.0 DCA ...................................................................................................................................... 239
8.1 Implementation Details ............................................................................................................ 239
8.1.1 PCIe* Message Format for DCA (MWr Mode) ......................................................................... 239