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Reset Operation — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 37
PCS_LCTL.FDV - Should be set by software to the duplex value established via software priority
resolution
PCS_LCTL.FLV - Should be set by software to 1b when software Auto-Negotiation completes
• Forced-Link (Auto-Negotiation Skipped) (PCS_LCTL. AN_ENABLE = 0b, and no software auto-
negotiation performed)
CTRL.FD - Duplex is set by software for the desired duplex mode of operation
CTRL.SLU - Must be set to 1b by software to enable communications to the SerDes
CTRL.RFCE - Set by software for the desired mode of operation
CTRL.TFCE - Set by software for the desired mode of operation
CTRL.SPEED - Set by software to desired link speed (must match speed setting of external SGMII PHY)
STATUS.FD - Reflects the value written by software to CTRL.FD
STATUS.LU - Reflects whether loss-of-signal (LOS) from SerDes is indicated, qualified with CTRL.SLU
(set to 1b)
STATUS.SPEED - Reflects MAC forced speed setting, written in CTRL.SPEED
PCS_LCTL.FORCE_LINK - Must be set to 1b by software to enable communications to the SerDes
PCS_LCTL.FSD - Must be set to 1b by software to enable communications to the SerDes
PCS_LCTL.FSV - Set by software to desired link speed (must match speed setting of external SGMII
PHY and CTRL.SPEED)
PCS_LCTL.FDV - Duplex is set by software for the desired duplex mode of operation (must match
duplex setting of external SGMII PHY and CTRL.FD)
PCS_LCTL.FLV - Must be set by software to 1b to enable communications to the SerDes
3.8 Reset Operation
The 82575’s reset sources are as follows:
PE_RST_N:
Asserting PE_RST_N indicates that both the power and the PCIe* clock sources are stable. This pin
asserts an internal reset also after a D3cold exit. Most units are reset on the rising edge of PE_RST_N.
The only exception is the GIO unit, which is kept in reset while PE_RST_N is deasserted (level).
Inband PCIe* Reset:
The 82575 generates an internal reset in response to a Physical layer message from the PCIe* or when
the PCIe* link goes down (entry to Polling or Detect state). This reset is equivalent to PCI reset in
previous (PCI) gigabit LAN controllers.