Filter
Top Products
Architectural Overview — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 21
2.0 Architectural Overview
This section provides an overview of the 82575. The following sections give detailed information about
the 82575’s functionality, register description, and initialization sequence. All major interfaces of the
82575 is described in detail.
The following principles shaped the design of the 82575:
1. Provide an Ethernet interface containing a 10/100/1000Mb/s PHY that also supports 1000 Base-X
implementations.
2. Provide the highest performance solution possible, based on the following:
— Provide direct access to all memory without using mapping registers
— Minimize the PIO accesses required to manage the 82575
— Minimize the interrupts required to manage the 82575
— Off-load the host processor from simple tasks such as TCP checksum calculations
— Maximize PCIe* efficiency and performance
3. Provide a simple software interface for basic operations.
4. Provide a highly configurable design that can be used effectively in different environments.
2.1 External Architecture
Figure 1 shows the external interfaces to the 82575.