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Flow Control Update Frequency — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 177
6.2.3 Flow Control Update Frequency
In any case, UpdateFC packets are scheduled immediately after a resource is available. When the Link
is in the L0 or L0s link state, Update FCPs for each enabled type of non-infinite flow control credit must
be scheduled for transmission at least once every 30 μs (-0% or +50%), except when the extended
synchronize bit of the control link register is set. In this case, the limit is 120 μs (-0% or +50%).
6.2.4 Flow Control Timeout Mechanism
The 82575 implements the optional flow control update timeout mechanism. This mechanism is
activated when the link is in L0 or L0s link state. It uses a timer with a limit of 200 μs (0% or +50%),
where the timer is reset by the receipt of any DLLP.
When the timer expires, the mechanism instructs the PHY to retrain the link through the LTSSM
recovery state.
6.2.5 Error Forwarding
If a TLP is received with an error forwarding trailer, the packet is dropped and is not delivered to its
destination.
System logic is expected to trigger a system level interrupt to inform the operating system of the
problem. The operating system has the ability to stop the process associated with the transaction, re-
allocate memory instead of the faulty area, etc.
6.3 Host Interface
6.3.1 Tag IDs
PCIe* device numbers identify logical devices within the physical device. The 82575 implements a
single logical device with up to two separate PCI functions: LAN 0 and LAN 1. The device number is
captured from each type 0 configuration write transaction.
Each of the PCIe* functions interfaces with the PCIe* unit through one or more clients. A client ID
identifies the client and is included in the tag field of the PCIe* packet header. Completions always carry
the tag value included in the request to allow routing of the completion to the appropriate client.
Tag IDs are allocated differently for read and write.
• For reads, Table 54 lists the Tag ID allocation. The Tag ID is interpreted by hardware in order to
forward the read data to the required device.
• For writes, Table 55 and Table 56 list the Tag ID allocation when DCA mode is not active. Unlike
reads, the values are for debug only enabling tracing of requests through the system. When in DCA
mode, the Tag IDs are replaced by the adequate DCA bits.
Note: Only five low bits of tags are usable because the configuration of the Extended Tag Field
Enable bit in the configuration space Device Control register (8h) depends on the operating
system and is not predictable.