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Intel
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82575EB Gigabit Ethernet Controller — Interrupt Moderation
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
166 January 2011
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (256 10
-9
sec interrupts/sec)
-1
The optimal performance setting for this register is very system and configuration specific. An initial
suggested value is 4000 (one interrupt every 250 s).
The EITR should default to 0b upon initialization and reset. It loads in the value programmed by the
software after software initializes the 82575.
When software wants to force an immediate interrupt, for example, after setting a bit in the EICR with
the EICS register, the value of the counter can be written to 0b to generate an immediate interrupt.
This write should include re-writing the Interval field with the desired constant, as it will be used to
reload the counter immediately for the next throttling interval.
The 82575 implements interrupt moderation to reduce the number of interrupts software processes.
The moderation scheme is based on EITR. Each time an interrupt event happens, the corresponding bit
in the EICR is activated. However, an interrupt message is not sent out on the PCIe* interface until the
EITR counter assigned to that EICR bit has counted down to zero. As soon as the interrupt is issued, the
EITR counter is reloaded with its initial value and the process repeats again. The interrupt flow should
follow as shown in Figure 20.