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Management Data Interface — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 269
11.5 Management Data Interface
The PHY supports the IEEE 802.3 MII Management Interface also known as the Management Data
Input/Output (MDIO) Interface. The MDIO interface consists of a physical connection to the MAC, a
specific protocol which runs across the connection, and a 16-bit MDIO register set.
PHY Registers 0d through 10d and 15d are required and their functions are specified by the IEEE 802.3
specification. Additional registers are included for expanded functionality.
11.6 Low Power Operation
The 82575 can be get into a low-power state according to MAC control (Power Management controls) or
via PHY register 0d. In either power down mode, the 82575 is not capable of receiving or transmitting
packets.
11.7 Power Down via the PHY Register
The PHY can be powered down using the control bit found in PHY register 0d, bit 11. This bit powers
down a significant portion of the port but clocks to the register section remain active. This enables the
PHY management interface to remain active during power-down. The power-down bit is active high.
When the PHY exits software power-down (PHY register 0d, bit 11 = 0b), it re-initializes all analog
functions, but retains its previous configuration settings.
11.8 1000 Mb/s Operation
This section provides an overview of 1000BASE-T functions, followed by discussion and review of the
internal functional blocks shown in Figure 30.