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10Base-T Link Failure Criteria and Override — Intel
®
82575EB Gigabit Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 275
11.10.2 10Base-T Link Failure Criteria and Override
Link failure occurs if Link Test is enabled and link pulses stop being received. If this condition occurs,
the PHY returns to the Auto-Negotiation phase if Auto-Negotiation is enabled. Setting PHY register 16d,
bit 14 disables the Link Integrity Test function, then the PHY transmits packets, regardless of link
status.
11.10.3 Jabber
If the MAC begins a transmission that exceeds the jabber timer, the PHY disables the transmit and
loopback functions and asserts collision indication to the MAC. The PHY automatically exits jabber mode
after 250-750 ms. This function can be disabled by setting PHY register 16d, bit 10 to 1b.
11.10.4 Polarity Correction
The PHY automatically detects and corrects for the condition where the receive signal (MDI_PLUS[0]/
MDI_MINUS[0]) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted
end-of-frame markers, are received consecutively. If link pulses or data are not received for 96-130 ms,
the polarity state is reset to a non-inverted state.
11.10.5 Dribble Bits
The PHY device handles dribble bits for all of its modes. If between one to four dribble bits are received,
the nibble is passed across the interface. The data passed across is padded with 1b’s if necessary. If
between five to seven dribble bits are received, the second nibble is not sent onto the internal MII bus
to the MAC. This ensures that dribble bits between 1-7 do not cause the MAC to discard the frame due
to a CRC error.
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