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Intel
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82575EB Gigabit Ethernet Controller — PCI Power Management Registers
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
208 January 2011
Reserved
Reserved. 2 bytes at offset B4h and is read only. Un-implemented reserved registers not relevant to
PCIe* endpoint.
The following two registers are implemented only if the capability version is 2.
Device CAP 2
Device Capability 2 is 4 bytes at offset C4h. This register identifies PCIe* device specific capabilities. It
is a read only register with the same value for the two LAN functions.
10 RO 0b Link Training Error
This indicates that a link training error has occurred.
9:4 RO 000001
b
Negotiated Link Width
This field indicates the negotiated width of the link.
Relevant encoding:
000001b = x1
000010b = x2
000100b = x4
3:0 RO 0001b Link Speed
This field indicates the negotiated link speed. A value of 0001b is the only defined speed, which
is 2.5 Gb/s.
Bit(s) RD/WR Default Description