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Rx DCA Control Registers - RXCTL (02814h 100h *n [n=0..3]; R/W) — Intel
®
82575EB Gigabit
Ethernet Controller
324632-003 Intel
®
82575EB Gigabit Ethernet Controller
Revision: 2.1 Software Developer’s Manual and EEPROM Guide
January 2011 377
• Queue3 - RXCTL3 (02B14h)
Field Bit(s)
Initial
Value
Description
CPUID 4:0 0h Physical ID
In a data movement engine 1 platform, the software device driver, upon discovery of
the physical CPU ID and CPU Bus ID, programs it into these bits for hardware to
associate Physical CPU and Bus ID with the adequate RSS Queue. Bits 2:1 are Target
Agent IDs, bit 3 is the Bus ID. Bits 2:0 are copied into bits 3:1 in the TAG field of the
TLP headers of PCIe* messages.
In data movement engine 2 platforms, the software device driver programs a value,
based on the relevant APIC ID, corresponding to the adequate RSS queue. This value is
copied in the 4:0 bits of the DCA Preferences field in the TLP headers of PCIe*
messages.
RX Descriptor
DCA EN
5 0b Descriptor DCA Enable
When set, hardware enables DCA for all Rx descriptors written back into memory.
When cleared, hardware does not enable DCA for descriptor write-backs. This bit is
cleared as a default.
Rx Header DCA
EN
6 0b Rx Header DCA Enable
When set, hardware enables DCA for all received header buffers. When cleared,
hardware does not enable DCA for Rx headers. This bit is cleared as a default.
Rx Payload DCA
EN
7 0b Payload DCA Enable
When set, hardware enables DCA for all Ethernet payloads written into memory. When
cleared, hardware does not enable DCA for Ethernet payloads. This bit is cleared as a
default.
RXdescRead
NSEn
8 0b Rx Descriptor Read No Snoop Enable
This bit must be reset to 0b to ensure correct functionality (unless the software device
driver can guarantee the data is present in the main memory before the DMA process
occurs).
RXdescRead
ROEn
9 0b Rx Descriptor Read Relax Order Enable
RXdescWBNSen 10 0b Rx Descriptor Write-Back No Snoop Enable
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
RXdescWBROen
(RO)
11 0b Rx Descriptor Write-Back Relax Order Enable
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
RXdataWrite
NSEn
12 0b Rx Data Write No Snoop Enable (header replication: header and data)
When set to 0b, the last bit of the Packet Buffer Address field in the advanced receive
descriptor is used as the LSB of the packet buffer address (A0), thus enabling 8-bit
alignment of the buffer.
When set to 1b, the last bit of the Packet Buffer Address field in advanced receive
descriptor is used as the No-Snoop Enabling (NSE) bit (buffer is 16-bit aligned). If also
set to 1b, the NSE bit determines whether the data buffer is snooped or not.
RXdataWrite
ROEn
13 1b Rx Data Write Relax Order Enable (header replication: header and data)
RxRepHeader
NSEn
14 0b Rx Replicated/Split Header No Snoop Enable
This bit must be reset to 0b to ensure correct functionality of header write to host
memory.
RxRepHeader
ROEn
15 1b Rx Replicated/Split Header Relax Order Enable
Reserved 31:16 0b Reserved