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Intel
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82575EB Gigabit Ethernet Controller — Half Duplex
Intel
®
82575EB Gigabit Ethernet Controller 324632-003
Software Developer’s Manual and EEPROM Guide Revision: 2.1
244 January 2011
9.2.2 Half Duplex
In half duplex mode, the 82575 attempts to avoid contention with other traffic on the wire, by
monitoring the carrier sense signal provided by the PHY, and deferring to passing traffic. When the
Internal Carrier Sense signal is deasserted or after sufficient InterPacket Gap (IPG) has elapsed after a
transmission, frame transmission can begin. The MAC signals the PHY with TX_EN at the start of
transmission.
In the case of a collision, the PHY/SGMII detects the collision and asserts the COL signal to the MAC.
Transmission of the frame stops within four link clock times, and the 82575 sends a JAM sequence onto
the link. After the end of a collided transmission, the 82575 backs off and attempt to retransmit per the
standard CSMA/CD method. Note that the re-transmissions are done from the data stored internally in
the 82575 MAC transmit packet buffer (no re-access to the data in host memory is performed).
The MAC behavior is different if a regular collision or a late collision is detected. If a regular collision is
detected, the MAC always tries to retransmit until the number of excessive collision is reached. In case
of late collision, the MAC retransmission is configurable. In addition, statistics are gathered on late
collisions.
In the case of a successful transmission, the 82575 is ready to transmit any other frame(s) queued in
the MAC’s transmit FIFO after the minimum Inter Frame Spacing (IFS) of the link has elapsed.
During transmit, the PHY is expected to signal a carrier-sense (assert the CRS signal) back to the MAC
before one slot time has elapsed. The transmission completes successfully even if the PHY fails to
indicate CRS within the slot time window; if this situation occurs, the PHY can either be configured
incorrectly or be in a link down situation. Such an event is counted in the Transmit without CRS statistic
register (see Section 14.8.12).
9.2.3 Gigabit Physical Coding Sub-Layer (PCS) for
SerDes
The 82575 integrates the 802.3z PCS function on-chip. The on-chip PCS circuitry is used when the link
interface is configured for Serdes or SGMII operation and is bypassed for internal PHY mode.
The packet encapsulation is based on the Fibre Channel physical layer (FC0/FC1) and uses the same
coding scheme to maintain transition density and DC balance. The physical layer device is the SerDes
and is used for 1000BASE-SX, -LX, or -CX configurations.
9.2.3.1 8B10B Encoding/Decoding
The Gigabit PCS circuitry uses the same transmission coding scheme used in the Fibre Channel physical
layer specification. The 8B10B coding scheme was chosen by the IEEE standards committee in order to
provide a balanced, continuous stream with sufficient transition density to allow for clock recovery at
the receiving station. There is a 25 percent overhead for this transmission code which accounts for the
data signaling rate of 1250 Mb/s with 1000 Mb/s of actual data.